1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to a mechanism for enabling and sustaining a multi-processor environment on a bus that requires active control of bus termination impedances, where the multi-processor environment includes processor package substrates having multiple processor dies disposed thereon.
2. Description of the Related Art
Many present day bus architectures provide only for a point-to-point bus interface between two devices such as a microprocessor and its corresponding memory controller in order to support very fast incident wave switching with a low output swing. In addition to providing only for a point-to-point interface, the architectures also require that the microprocessor (or other device) provide termination impedance control circuits within to dynamically adjust a termination impedance on the point-to-point bus, where the value of the impedance is generally selected to match the characteristic impedance of the bus itself.
In many applications, the value of the impedance is communicated to the device by coupling a precision resistor to an I/O pin on the device. Accordingly, the device provides drivers on-die that are configured to drive the point-to-point bus at the selected impedance value and at voltage levels in accordance with the bus specifications. These drivers provide for a properly terminated transmission line that supports the minimization of reflections, signal distortion, and other transmission line effects.
And while the point-to-point bus is effective for the case where only two devices communicate over the bus, the present inventors have noted for certain application areas such as a multi-processor application, more than one device may be required. In these applications, perhaps one to eight processors are required to interface in parallel to a memory controller over a bus as described above. In the future, it is anticipated that many more processors will be required to communicate over the same bus.
In U.S. Pat. No. 7,358,758, entitled APPARATUS AND METHOD FOR ENABLING A MULTI-PROCESSOR ENVIRONMENT ON A BUS, the present inventors addressed the above-noted problem by disclosing techniques for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus was provided for enabling a multi-device environment on a bus, where the bus requires active termination impedance control. The apparatus included a first node, configured to receive an indication that a corresponding device is at a physical end of the bus or that the corresponding device is an internal device. The apparatus also included multi-processor logic; coupled to the first node, configured to control how a second node is driven according to the indication, where the second node is coupled to the bus. The multi-processor logic enables pull-up logic and pull-down logic if the indication indicates that the corresponding device is at the physical end of the bus. The multi-processor logic disables the pull-up logic and enables the pull-down logic if the indication designates the corresponding device as an internal device. The pull-down logic drives the second node to a prescribed low voltage level regardless of whether the pull-up logic is enabled or disabled.
With the advent of so-called multi-core architectures, the present inventors have further noted a need in the art to address the need for active termination impedance control for a plurality of processor cores that are coupled together over a bus to a memory controller or other device, where the processor cores are each configured as a single processor die, and where two or more of these single processor dies are disposed on a single substrate within a multi-core processor package that is coupled to the bus. For purposes of the present disclosure, the term “multi-core processor” is defined to mean two or more single processor dies which are disposed on a single substrate. The single substrate may be multiple layers of interconnecting signals and other devices that provide for packaging of the multi-core processor and connectivity to the bus and other system-related signals.
The present inventors have moreover observed a need in the art to address the need for active termination impedance control for a plurality of multi-core processor packages, as described above, that are coupled together over a bus to a memory controller or other device.
But conventional bus architectures are limited because they require active impedance control without provisions for the use of multi-core processors. For example, when one processor core drives the bus described above, it would see an effective termination impedance that is developed by the parallel termination impedances of the other processor cores on the bus in addition to the other bus devices and, accordingly, driving I/O signals into this effective pull-up termination impedance would result in high frequency noise, reflections, ringing, timing displacements, and other disadvantages.
Consequently, the present inventors have observed that it is highly desirable to provide for inter-operation of a variable number of devices over a bus that requires active impedance control, where those devices include multi-core processors.
In addition, the present inventors have noted a need in the art for enabling a multi-core/multi-package environment over an actively controlled bus.